Implementing Image Processing Algorithms in FPGA Using VHDL High Level Languages & Vivado ESL (PPT). IMPLEMENTATION OF IMAGE PROCESSING ALGORITHMS ON FPGA HARDWARE http://isis.vanderbilt.edu/sites/default/files/Nelson_T_0_0_2000_Implementa.pdf http://www.mouser.tw/pdfdocs/Terasic_CLR_HSMC_User_Manual.pdf Building Zynq Accelerators with Vivado High Level Synthesis Altera 的HLS 是C2H http://www.altera.com/literature/tt/tt_nios2_c2h_accelerating_tutorial.pdf Altera DE2-115 教育開發平台 http://www.61ic.com/code/attachment.php?aid=52716&k=0e1af4c4bbf7b4e09a251c6088b66130&t=1301316753 Altera Nios II 嵌入式系統開發套件 ftp://ftp.altera.com/up/pub/Altera_Material/10.1/Tutorials/Altera_Monitor_Program.pdf This tutorial presents an introduction to the Altera Monitor Program, which can be ... the Monitor Program commands described in the tutorial, it should still be ... Introduction to the Altera Monitor Program Nios II Embedded Processors for Education http://ei.hust.edu.cn/teacher/zengyj/2013/EI0821361/Reading%20Assignments/DE2_UserManual_Chinese.pdf https://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=China&No=564&FID=ff67ea369f4b2acaa5b0c1e46399bdf0 Embedded Image Processing on the TMS320C6000TM DSP http://books.google.com.tw/books?id=w3BZ0PrmqtkC&pg=PA208&lpg=PA208&dq=tms320c6000+programmer%27s+guide+VIDEO&source=bl&ots=CkpzXAfLD-&sig=AEqjjXjpW-WquzufBA8lZxlHeG8&hl=zh-TW&sa=X&ei=QkD8U5jOHtHi8AWru4HoBQ&ved=0CC8Q6AEwAg#v=onepage&q=tms320c6000%20programmer's%20guide%20VIDEO&f=false Code Composer Studio http://gigazine.net/news/20140512-phenox/ http://phenoxlab.com/?lang=ja Introduction to FPGA Design with Vivado High-Level Synthesis Software based Finite State Machine (FSM) with general purpose processors Runtime Dependency Analysis for Loop Pipelining in High-Level Synthesis